Not applicable.
1. Field of Invention
This invention relates to high speed switching, specifically, of currents in an integrated circuit.
2. Description of Prior Art
High speed switching of a current in an integrated circuit is very important in numerous applications. For example, digital-to-analog converters are often designed using currents which are switched in or out, and the speed of settling is an important metric in performance of these so-called IDACs. In Phase Locked Loops, high speed current switching is often used as part of the timing circuits. In U.S. Pat. No. 4,677,323, FIG. 1, a current reference 100 and a pair of reference transistors 102,104 connect to a current mirror transistor 106. A FET switch 108 is placed between the source of an FET current mirror transistor 106 and the power supply line. When the switch is toggled on and off, the current source is turned on and off. The current source transistor 106 acts like a cascode structure isolating the transitions at the gate of the switch from the load to which the current is being sent. This isolation reduces the transient error seen by the load and makes settling time faster than previous approaches. One concern with this patent is that if the switch is off for any long period of time, the drain of the switch transistor is free to float. This could require a relatively long time to turn the switch on, and a relatively large drain transient, both of which degrade performance.
In U.S. Pat. No. 5,767,736, the gate of the current source 200 is switched between the gates one of two current reference transistors 202,206. One of the references is the current source 204 the circuit intends to generate at his output when the current source is on. The other 208 is much lower current, typically on the order of a few percent of the first reference 204. The effect is that the gate is only switched through a relatively small voltage instead of the more conventional approach wherein the gate is switched from the current reference to the power rail. All gate transitions are small and well controlled, which is desired. However, the gate capacitance is charged through the on resistance of the switch, and if the switch is large for low on resistance, the transient voltage at the gate of the switch is coupled across its gate to drain capacitance to the gate of the current source transistor, and then through the gate to drain capacitance of the current source transistor to the output. Furthermore, the off state of the switch is not off, which adds error in some applications. Yet another deficiency to this approach is that the charge needed to charge the gate capacitance comes from the reference current source. On chip filtering is needed to ensure that the switch transients do not couple into other current sources being driven from the same reference.
U.S. Pat. No. 6,160,432 is another high speed current switch. This patent adds a cascode to the output of either of the above discussed patents. While this isolates charge feed through from the switching operation to the output, it does not address the floating source concern with the first of the gate charging of the second.
In accordance with the present invention, the switch for the current source is placed between the source of the current source transistor and the power rail, as in U.S. Pat. No. 4,677,323. Means are added to limit the movement of the source when the switch is turned off. Means are also added to cancel any remaining output current when the switch turns off.
Accordingly, several objects and advantages of this invention are:
(a) very high speed current source switching is achieved;
(b) Charge for the switch operation comes from the power rail thereby providing good isolation between current sources;
(c) transient switching errors are isolated from the output by a cascode structure; and
(d) error current due to finite off current is very low.